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Workshop on Automatic Tuning for Petascale Systems

by admin last modified 2007-10-31 02:40

Held July 9-12, 2007, Snowbird Ski & Summer Resort, Snowbird, Utah, USA

Workshop Agenda:: Workshop Slides

 

Organizers

  • Kathy Yelick (University of California at Berkeley), "yelick"  AT "cs.berkeley.edu"

  • Keith Cooper (Rice University), "keith" AT "cs.rice.edu"

Abstract


Over the past several years, processors have grown in complexity due to the inclusion of multiple cores, processor accelerators, and various techniques to mask the ever-growing gap between on-chip computation performance and off-chip memory access performance. Each of these performance features requires a significant effort in tuning of applications and libraries.  As a result, compiler and library developers have turned to automating the process of software tuning, using large amounts of computation time to explore a space of different variants of the program and running each variant on the target architecture.  
The goal of this workshop was to bring together researchers and practitioners in automatic tuning, compiler code generation, and architecture design to identify some of the opportunities and challenges of using automatic tuning on future petascale systems. The emphasis was on optimizations for multicore processors, accelerators, and novel computational and memory structures that will make up the compute nodes of petascale systems.

Agenda

Day 1 - Monday, July 9

Day 2 - Tuesday, July 10


Day 3 - Wednesday, July 11

Day 4 - Thursday, July 12


Sponsors

This workshop was sponsored by the Center for Scalable Application Development Software, with funding from the DOE Office of Science through the Scientific Discovery through Advanced Computing (SciDAC) program.

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CScADS Collaborators include:

Rice University ANL UCB UTK WISC