The Sony/Toshiba/IBM (STI) CELL processor introduces pioneering solutions in processor architecture. At the same time, it presents new challenges for the development of numerical algorithms. One is the effective exploitation of the differential between the speed of single- and double-precision arithmetic; the other is the efficient parallelization between the short-vector Single-Instruction, Multiple-Data (SIMD) cores. The first challenge is addressed by utilizing the well-known technique of iterative refinement for the solution of a dense symmetric positive definite system of linear equations, resulting in a mixed-precision algorithm, which delivers double-precision accuracy while performing the bulk of the work in single precision. The main contribution of this paper lies in addressing the second challenge by successful thread-level parallelization, exploiting fine-grained task granularity and a lightweight decentralized synchronization. The implementation of the computationally intensive sections gets within 90 percent of the peak floating-point performance, while the implementation of the memory-intensive sections reaches within 90 percent of the peak memory bandwidth. On a single CELL processor, the algorithm achieves more than 170 Gflops when solving a symmetric positive definite system of linear equations in single precision and more than 150 Gflops when delivering the result in double-precision accuracy.