Organizers

• Jack Dongarra (University of Tennessee at Knoxville), "dongarra" AT "cs.utk.edu"
• Keith Cooper, "keith" AT "cs.rice.edu"
• Rich Vuduc, "richie" AT "cc.gatech.edu"
• Kathy Yelick, "yelick" AT "eecs.berkeley.edu"

Abstract

Over the last decade, microprocessor features such as deep pipelines, multiple cores, and complex memory hierarchies have made it increasingly difficult to achieve good performance in scientific applications and libraries. This fact has given rise to systems that automate the tuning process, using large amounts of computation to configure the application or library for good performance on the target architecture.

This workshop, the third in the series, will bring together researchers and practitioners in automatic tuning, in library design and construction, and in compiler-based code generation to identify and discuss opportunities and challenges in the use of automatic tuning for future petascale systems. As with last year, we are actively soliciting members of the compiler and library autotuning communities. In addition, we are interested in attracting attendees whose focus is on runtime optimization of scientific programs.

The workshop will consist of a series of talks and discussion sessions. We anticipate that most workshop attendees will present a talk on their research, their insights, and their experience. The discussion sessions will focus on opportunities to build shared infrastructure, along with issues raised during the workshops.

Sponsors

This workshop is sponsored by the Center for Scalable Application Development Software, with funding from the Scientific Discovery through Advanced Computing (SciDAC) program.

Agenda

[Final Agenda + Slides]

Draft Agenda